TDM serial streams often have to be synchronized with each other for correct operation. Typical synchronizing timing signals employed in TDM switching is an 8 kHz timing signal also referred to as a frame pulse. Typically, every 8 bits makes up one channel and each serial stream has a fixed number of channels every frame (125 microseconds). For example, 2.048 Mb/s stream has 32 channels per frame and 8.192 Mb/s stream has 128 channels per frame. Usually, all channels of one frame need to be stored into internal memory so that the data can be switched on a per frame basis (8 kHz).
Because multiple data rates are typically employed for TDM streams such as 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s, 16.384 Mb/s, 32.768 Mb/s and even higher rates, rate conversion switches are required to convert data between different data rates. The prior art method of performing rate conversion is to reserve the maximum number of memory locations for the stream having the highest data rate of all of the streams which appear at the switch. Thus, if data streams having a range of rates from, for example, 2.048 Mb/s to 16.384 Mb/s, 256 memory locations per frame would need to be reserved. Thus when a 2.048 Mb/s data stream is received requiring only 32 channels the high number of reserved locations leads to wasted memory. This results in a low efficiency of memory usage and it will be apparent from the above that the higher the data rate the less efficient the memory usage will be.
The present invention overcomes the memory waste problem by allocating memory addresses dynamically by using a virtual counter. In this way the full switching bandwidth provided by the internal memory can always be available no matter what data rate is employed.